Amy Apon
Major contributor to the research conducted with the High Performance Computing Center at the University of Arkansas and currently working to provide the University community with a new supercomputer that will supersede “Red Diamond.”
Jia Di
Delay-Insensitive Asynchronous 8051-Compliant Microcontroller Design for Extreme Temperatures
Ultra-wide temperature (-180 °C to +130 °C) and low temperature (-230 °C) electronics will reduce size and weight of current systems while at the same time improving the reliability and efficiency of those systems by reducing the need for thermal control and shielding. Since the physical parameters of transistors change dramatically when subjected to ultra-wide temperature swings, it significantly affects the transistors’ behavior, including their switching speed. As a result, the timing characteristics of different circuit blocks within a digital system vary widely with temperature, causing timing constraints violations and clock skews in synchronous circuits. Developing microcontrollers based on asynchronous logic will significantly improve wide temperature performance. Delay-insensitive asynchronous circuits remove the concept of a global clock by incorporating handshaking protocols to control the circuit. Theoretically, as long as the transistors can switch properly, the asynchronous circuits will always function correctly. Another important advantage of asynchronous circuits is their potential for low power consumption: these circuits are able to operate correctly under a much lower supply voltage under low temperatures without worrying about resulted timing variations, which may cause synchronous circuits to malfunction.
Towards Trustable Embedded Systems: Hardware Threat Modeling for Integrated Circuits
The impact of software viruses has been felt by the entire computerized world. Hardware, especially integrated circuits, was considered safe and attack-free, in contrast to its software counterpart. However, as technologies advance and markets expand, hardware is becoming vulnerable like software. Malicious logic, similar to a software virus, could be inserted into a circuit like a Trojan horse such that it lies dormant and is very difficult to detect until activated, but then cannot be effectively defeated. These days most complex digital systems are not designed from scratch; instead they use many 3rd party Intellectual Property (IP) blocks. Hence, one or more 3rd party IP blocks could contain malicious logic that may affect the entire system. Furthermore, all non-trivial digital designs rely heavily on Computer-Aided Design (CAD) tools. These CAD tools themselves may be contaminated or malevolently configured, causing them to insert malicious logic into circuits. The goal of this research is to develop a prototype automated hardware threat modeling algorithm/tool to model potential hardware threats/attacks of digital integrated circuits in embedded systems, and analyze their trustability.
Mitigating Side-Channel Attacks to Digital ICs
As part of the anti-counterfeiting RFID tags project, this research is to mitigate power- and timing-based side-channel attacks. In contrast to invasive attacks to digital ICs, side-channel attacks do not require the target to be physically de-packaged. Instead, attackers can monitor the fluctuations of certain external parameters such as power consumption and timing delay caused by different data being processed. The recorded data will be analyzed to calculate the desired information. This project is to develop a power-/timing-attack mitigation technique by designing digital ICs using Dual-spacer Dual-rail Delay-insensitive asynchronous Logic (D3L) to balance the power consumption and obfuscate the timing delays among different data patterns, thus rendering these attacks useless. Three versions of the Advanced Encryption Standard (AES) core, namely, synchronous, traditional delay-insensitive asynchronous (NULL Convention Logic), and D3L, will be designed, attacked, and compared. The results will be analyzed for the effectiveness and efficiency of the mitigation.
Asynchronous Cell Matrix for Nanocomputing
One exciting anticipated outcome of nanotechnology is the ability to construct systems with many orders of magnitude more components. This truly remarkable expansion of physical hardware must be met by innovation in computing architecture. The question is how to effectively and efficiently integrate, configure, and utilize these trillion×trillion components available. Cell Matrix, developed by Cell Matrix Corp., is a construction of physically homogeneous, reconfigurable hardware components, which are connected in a regular structure topology and configured to implement a desired digital circuit. This architecture could be used to implement dynamic, massively parallel, self-modifying/-repairing/-healing circuits. However, the current synchronous Cell Matrix requires clocks, which are not feasible for extremely large systems. The goal of this research is to develop a dynamically fault-tolerant asynchronous Cell Matrix that communicates using delay-insensitive handshaking in lieu of clocks and is able to modify itself to mitigate faults, autonomously moving functionality from faulty cells and rerouting to retain complete system operability.
Susan Gauch
Next Generation CiteSeer
CiteSeer is a scientific literature digital library and search engine which automatically crawls and indexes scientific documents in the field of computer and information science. It has over 730,000 documents with over 8 million citations. The Next Generation CiteSeer or CiteSeerX initiative aims at enhancing the existing search engine by redesigning the architecture for increased utility and reliability and expanding the breadth and depth of the collection. This joint effort between the Penn State University and the University of Arkansas is primarily funded by the National Science Foundation. The efforts here at the University of Arkansas focus on designing and developing new personalization features for CiteSeer based on conceptual user profiles.
Semi-Automated Construction of an Ontology for Amphibian Morphology
The integration of information across remote systems is becoming more and more important. This is the core exchange problem addressed by the Semantic Web. Because they can be used either by software agents or by humans, these technologies commonly exploit ontologies as the vehicle for information exchange. Currently, the use of ontologies requires large amounts of manual effort. We believe that the Semantic Web will be more widely available once we are able to handle ontologies more easily. In this joint project with the Missouri University of Science and Technology, we are constructing a system that reduces the amount of human effort required by semi-automatically creating an ontology. We will demonstrate this approach in the domain of vertebrate morphology. If successful, this approach could be applied to other domains, increasing the adoption of concept based applications.
Wing-Ning Li
Algorithms for computing path based optimal measure of social network
Given a social network as a weighted graph, the relationship between two organizations or individuals could be measured by the optimal path between the corresponding vertices. The value of a path between two vertices could be defined in many ways such as the minimum edge weight of the path divided by the number of edges in the path, the total weight of the path divided by the length of the path. An optimal path is a path that has the largest value among all possible paths between two vertices. How do we find such optimal paths between each pair efficiently?
Helen Shen
Research on P2P networks solving problems involving congestion control inherent in these networks due to the nature of heterogeneity, dynamism of network nodes and skewed lookups.
Dale R. Thompson
Research on anti-counterfeiting RFID tags, the objective of the anti-counterfeiting RFID tag research is to prevent counterfeiting of RFID tags by offering mitigating techniques that provide different levels of protection and have different requirements in cost and implementation complexity in order to provide appropriately secure and flexible solutions for different applications. The anticipated results of this high-risk and high-payoff area of research are cost-effective and reliable anti-counterfeiting techniques to prevent cloning of RFID tags.
Brajendra Panda
Currently, we are working on two major research projects. The first one involves designing security protocols that preserve data confidentiality and integrity. One of the primary objectives of this project is to develop adjustable security policies that account for balancing the tradeoff between system security and information availability. Using such policies we wish to provide novel security mechanisms for developing survivable information systems.
The second project relates to data provenance. Use of corrupt or untrustworthy data in critical applications can have devastating results. In order to provide information reliability, the methods used to acquire and process data, in addition to the source of the data, must be trustworthy. Key tasks of this project include identification and propagation of the data provenance methods, and storage, retrieval, and analysis of such information.
